• Verification planning & strategy

  Verification plan, coverage model and sign-off criteria, written from your specification and agreed with your team up front.

• UVM testbenches

  Built from scratch or extended from yours, from IP to subsystem level, with scoreboards and bit-exact checking against MATLAB or C reference models.

• Verification IP

  New UVM agents built for your protocols and interfaces, and reuse of commercial or in-house VIP in your testbenches.

• SoC & integration verification

  Top-level tests and C tests running on embedded ARM and RISC-V CPUs.

• Formal verification

  Formal property verification, coverage unreachability analysis, connectivity checking, and datapath checking against C models (Jasper C2RTL).

• Coverage closure & sign-off

  Code and functional coverage closure, regression triage and pass/fail rate closure, X-propagation and gate-level simulation.

Proven tapeout track record, from IP blocks to top level.

What we verify

• Digital ASICs
• Digital side of mixed-signal ASICs
• FPGAs

Application areas

• 5G radio (digital front-end)
• Software-defined radio
• Display controllers (MIPI)
• Digital signal processing
• High-performance computing

Methods

• UVM
• SVA
• Formal verification
• Constrained-random
• Metric-driven verification
• Firmware-driven verification

Languages

• SystemVerilog
• VHDL
• C
• Python
• MATLAB

Tools

Toolchains from all three major EDA vendors, plus FPGA tooling:

• Cadence
• Synopsys
• Siemens
• AMD Vivado

CPU architectures

• ARMv7-M
• RISC-V

Protocols

• AXI
• AXI-Stream
• AHB
• APB
• MIPI DSI-2
• MIPI C-PHY
• MIPI D-PHY
• SPI
• UART
• I2C

• Remote contract

  Part of your team, working remotely, billed hourly or daily.

• Fixed-scope projects

  A defined deliverable, for example a verification plan or a complete testbench, at an agreed price.

• On site when needed

  For kickoffs and critical project phases.

Hire us for your next project.